FIG. 1A is a schematic circuit diagram illustrating a conventional differential cell. As shown in FIG. 1A, the differential cell c1 comprises two sub-cells cx and cy. Each of the sub-cells cx and cy comprises a floating gate transistor. Consequently, the differential cell c1 is a floating gate type differential cell.
The sub-cell cx comprises a floating gate transistor M1. The sub-cell cy comprises a floating gate transistor M2. A control terminal of the floating gate transistor M1 is connected with a word line WL. A drain terminal of the floating gate transistor M1 is connected with a bit line BL. A source terminal of the floating gate transistor M1 is connected with a source line SL. A control terminal of the floating gate transistor M2 is connected with the word line WL. A drain terminal of the floating gate transistor M2 is connected with an inverted bit line BLb. A source terminal of the floating gate transistor M2 is connected with an inverted source line SLb. When proper bias voltages are provided to the word line WL, the bit line BL, the inverted bit line BLb, the source line SL and the inverted source line SLb, a program action or a read action is performed on the differential cell c1.
While the program action is performed on the differential cell c1, the sub-cells cx and cy of the differential cell c1 are in a complementary state. For example, in case that the sub-cell cx is programmed to an on state, the sub-cell cy is programmed to an off state. Whereas, in case that the sub-cell cx is programmed to the off state, the sub-cell cy is programmed to the on state.
While the read action is performed on the differential cell c1, the word line WL is activated. When the word line WL is activated, the sub-cell in the on state generates a higher cell current and the sub-cell in the off state generates a lower cell current. The cell current generated by the sub-cell in the off state is nearly zero. According to the result of comparing the cell currents from the two sub-cells, the storage state of the differential cell c1 is determined. Generally, the cell current is a read current during the read cycle.
In case that the sub-cell cx is programmed to the on state and the sub-cell cy is programmed to the off state during the program cycle, the read current Ix from the sub-cell cx is higher than the read current Iy from the sub-cell cy during the read cycle. Under this circumstance, the differential cell c1 is judged to be in a first storage state.
In case that the sub-cell cx is programmed to the off state and the sub-cell cy is programmed to the on state during the program cycle, the read current Ix from the sub-cell cx is lower than the read current Iy from the sub-cell cy during the read cycle. Under this circumstance, the differential cell c1 is judged to be in a second storage state.
In FIG. 1A, the sub-cell cx comprises the n-type floating gate transistor M1, and the sub-cell cy comprises the n-type floating gate transistor M2. In practice, the differential cell c1 has other structures. For example, the differential cell is a floating gate type differential cell comprising two p-type floating gate transistors, or the differential cell is an antifuse type differential cell comprises two antifuse type transistors.
FIG. 1B is a schematic circuit diagram illustrating a memory cell array comprising differential cells. The memory cell array 110 comprises m×n differential cells c11˜cmn.
In the memory cell array 110, m word lines WL1˜WLm are connected with the corresponding m rows of n differential cells. The n differential cells in the same row are connected with n bit line pairs (BL1, BLb1)˜(BLn, BLbn) and n source line pairs (SL1, SLb1)˜(SLn, SLbn). Each bit line pair comprises a bit line and an inverted bit line. Each source line pair comprises a source line and an inverted source line.
For example, the differential cell c11 in the first row is connected with the word line WL1, the bit line pair (BL1, BLb1) and the source line pair (SL1, SLb1). The connecting relationships between the other differential cells c12˜c1n and the associated lines are similar to the connecting relationships between the differential cell c11 and the associated lines, and are not redundantly described herein.
During a program cycle, one of the m word lines WL1˜WLm is activated. The row corresponding to the activated word line is referred as a selected row. The n differential cells in the selected row are referred as selected differential cells. In addition, the n differential cells are programmed. While the program action is performed, the two sub-cells of each selected differential cell of the selected row are programmed to be in the complementary state.
During a read cycle, one of them word lines WL1˜WLm is activated and a selected row is determined. Meanwhile, each selected differential cell of the selected row generates read currents to the corresponding bit line pair. According to the result of comparing the read currents of the bit line pair with each other, the storage state of the corresponding differential cell is determined.
During the read cycle of the conventional memory cell array and an activation period of one word line, each selected differential cell of the selected row generate read currents to the corresponding bit line and the corresponding inverted bit line. When the activation period of the word line is ended, the selected differential cell stops generating the read currents.